Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms - Network and Parallel Computing Access content directly
Conference Papers Year : 2018

Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms

Abstract

As the depth of DNN increases, the need for DNN calculations for the storage and computing power of the underlying computing platform is increasing. In this work, we implement an accelerator on FPGA for deep learning algorithms (CNN and RNN). The core computing module of the accelerator is a 32 * 32 systolic array of PEs. A mapping method for variable size of CNN and RNN algorithms is proposed. The experiment result shows that the maximum power consumption of the accelerator is 7.5W@100Mhz, the peak performance is 0.2Tops/s, and the real performance is 7.6Mops@100Mhz when running the 1st layer of LeNet-5.
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hal-02279547 , version 1 (05-09-2019)

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Zhijie Yang, Lei Wang, Dong Ding, Xiangyu Zhang, Yu Deng, et al.. Systolic Array Based Accelerator and Algorithm Mapping for Deep Learning Algorithms. 15th IFIP International Conference on Network and Parallel Computing (NPC), Nov 2018, Muroran, Japan. pp.153-158, ⟨10.1007/978-3-030-05677-3_16⟩. ⟨hal-02279547⟩
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