Statistical Evaluation of Digital Techniques for <math xmlns=""> <mi>&#x03A3;<!-- Σ --></mi> <mi>&#x0394;<!-- Δ --></mi> </math> ADC BIST - VLSI-SoC: Internet of Things Foundations Access content directly
Conference Papers Year : 2015

Statistical Evaluation of Digital Techniques for Σ Δ ADC BIST


Digital techniques for an embedded dynamic test of Σ Δ ADCs have been recently presented in the literature. These techniques are based on the use of Σ Δ streams for the stimulation of the ADC. Binary and ternary test stimuli have been proposed. In this chapter, we aim at the validation of these embedded test techniques, comparing the results obtained with the different types of digital stimuli with a standard high-resolution analog sinusoidal stimulus. This validation is done in terms of the expected yield loss and test escapes of the proposed embedded techniques. However, performing this validation at the design stage demands extensive computational resources, which may render electrical simulations infeasible. Thus, we propose an advanced simulation framework for this validation. The proposed simulation strategy relies on a combination of transistor-level simulations, behavioral simulations, and statistical tools.
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Dates and versions

hal-01383733 , version 1 (19-10-2016)





Matthieu Dubois, Haralampos-G. Stratigopoulos, Salvador Mir, Manuel J. Barragan. Statistical Evaluation of Digital Techniques for Σ Δ ADC BIST. 22th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC 2014), Oct 2014, Playa del Carmen, Mexico. pp.129-148, ⟨10.1007/978-3-319-25279-7_8⟩. ⟨hal-01383733⟩
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