Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture - VLSI-SoC: Internet of Things Foundations Access content directly
Conference Papers Year : 2015

Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture

Dongwoo Lee
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  • PersonId : 990871
Kiyoung Choi
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  • PersonId : 990872

Abstract

This chapter presents a technique for reducing energy consumed by hybrid caches that have both SRAM and STT-RAM (Spin-Transfer Torque RAM) in multi-core architecture. It is based on dynamic way partitioning of the SRAM cache as well as the STT-RAM cache. Each core is allocated with a specific number of ways consisting of SRAM ways and STT-RAM ways. Then a cache miss fills the corresponding block in the SRAM or STT-RAM region based on an existing technique called read-write aware region-based hybrid cache architecture. Thus, when a store operation from a core causes an L2 cache miss (store miss), the block is assigned to the SRAM cache. When a load operation from a core causes an L2 cache miss (load miss) and thus causes a block fill, the block is assigned to the STT-RAM cache. However, if all the allocated ways are already placed in the SRAM, then the block fill is done into the SRAM regardless of store or load miss. The partitioning decision is updated periodically. We further improve our technique by adopting the so called allocation switching technique to avoid too much unbalanced use of SRAM or STT-RAM. Simulation results show that the proposed technique improves the performance of the multi-core architecture and significantly reduces energy consumption in the hybrid caches compared to the state-of-the-art migration-based hybrid cache management.
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hal-01383728 , version 1 (19-10-2016)

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Dongwoo Lee, Kiyoung Choi. Energy-Efficient Partitioning of Hybrid Caches in Multi-core Architecture. 22th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC 2014), Oct 2014, Playa del Carmen, Mexico. pp.58-74, ⟨10.1007/978-3-319-25279-7_4⟩. ⟨hal-01383728⟩
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