Automated Functional Verification of Application Specific Instruction-set Processors - Embedded Systems: Design, Analysis and Verification Access content directly
Conference Papers Year : 2013

Automated Functional Verification of Application Specific Instruction-set Processors

Marcela Šimková
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  • PersonId : 1001361
Zdeněk Přikryl
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  • PersonId : 1001362
Zdeněk Kotásek
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  • PersonId : 1001363
Tomáš Hruška
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Nowadays highly competitive market of consumer electronics is very sensitive to the time it takes to introduce a new product. However, the ever-growing complexity of application specific instruction-set processors (ASIPs) which are inseparable parts of nowadays complex embedded systems makes this task even more challenging. In ASIPs, it is necessary to test and verify significantly bigger portion of logic, tricky timing behaviour or specific corner cases in a defined time schedule. As a consequence, the gap between the proposed verification plan and the quality of verification tasks is widening due to this time restriction. One way how to solve this issue is using faster, efficient and cost-effective methods of verification. The aim of this paper is to introduce an automated generation of SystemVerilog verification environments (testbenches) for verification of ASIPs. Results show that our approach reduces the time and effort needed for implementation of testbenches significantly and is robust enough to detect also well-hidden bugs.
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Dates and versions

hal-01466668 , version 1 (13-02-2017)





Marcela Šimková, Zdeněk Přikryl, Zdeněk Kotásek, Tomáš Hruška. Automated Functional Verification of Application Specific Instruction-set Processors. 4th International Embedded Systems Symposium (IESS), Jun 2013, Paderborn, Germany. pp.128-138, ⟨10.1007/978-3-642-38853-8_12⟩. ⟨hal-01466668⟩
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