index - Equipe Secure and Safe Hardware

 

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AES Switches Side-channel analysis Side-Channel Analysis Reverse-engineering Coq OCaml Receivers Writing Asynchronous Authentication Loop PUF Energy consumption Power demand Memory Controller Magnetic tunnel junction Application-specific VLSI designs Side-channel attacks SCA FDSOI Resistance Field programmable gate arrays Security and privacy Field Programmable Gates Array FPGA Dual-rail with Precharge Logic DPL Sensors Convolution Logic gates Information leakage Security Simulation Lightweight cryptography Fault injection EMFI Hardware security Countermeasure Cryptography Machine learning PUF Image processing Electromagnetic RSA Formal proof SCA Power-constant logic Filtering Temperature sensors Fault injection attack Formal methods Side-Channel Attacks Signal processing algorithms Side-Channel Analysis SCA Elliptic curve cryptography Intrusion detection Random access memory CPA Fault attacks ASIC Reliability Confusion coefficient Transistors Defect modeling Randomness TRNG Training Circuit faults Differential power analysis DPA Process variation Estimation Side-channel attacks Embedded systems Magnetic tunneling Robustness 3G mobile communication Neural networks Routing SoC Countermeasures Masking countermeasure MRAM Mutual Information Analysis MIA STT-MRAM Side-channel attack Gem5 Dynamic range DRAM GSM Security services Protocols Linearity CRT Aging FPGA Reverse engineering Hardware Voltage Computational modeling Differential Power Analysis DPA Masking Costs Internet of Things

 

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