Translation Validation for Synchronous Data-Flow Specification in the SIGNAL Compiler - Formal Techniques for Distributed Objects, Components, and Systems
Conference Papers Year : 2015

Translation Validation for Synchronous Data-Flow Specification in the SIGNAL Compiler

Van Chan Ngo
  • Function : Author
  • PersonId : 1030896
Efficient STAtistical methods in SYstems of systems
Jean-Pierre Talpin
Tim, Events and Architectures
Thierry Gautier
Tim, Events and Architectures
CV

Abstract

We present a method to construct a validator based on translation validation approach to prove the value-equivalence of variables in the compilation of the Signal compiler. The computation of output signals in a Signal program and their counterparts in the generated C code is represented by a Synchronous Data-flow Value-Graph (Sdvg). Our validator proves that every output signal and its counterpart variable have the same values by transforming the Sdvg graph.

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Computer Science [cs] Networking and Internet Architecture [cs.NI]
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Submitted on : Monday, April 16, 2018-10:18:48 AM

Last modification on : Wednesday, November 6, 2024-1:00:02 PM

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hal-01767328 , version 1 (16-04-2018)

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Van Chan Ngo, Jean-Pierre Talpin, Thierry Gautier. Translation Validation for Synchronous Data-Flow Specification in the SIGNAL Compiler. 35th International Conference on Formal Techniques for Distributed Objects, Components, and Systems (FORTE), Jun 2015, Grenoble, France. pp.66-80, ⟨10.1007/978-3-319-19195-9_5⟩. ⟨hal-01767328⟩

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