The design of today’s embedded systems requires a complex verification process. In particular, due to the strong hardware/software interdependence, debugging the embedded software is a demanding task. We have previously reported our results about the development of a framework that enables the Assertion-Based Verification (ABV) of temporal requirements for high-level reference models of such systems. In this paper, we describe conceptual and practical improvements of this monitoring infrastructure to give the user the possibility to customize and to optimize the verification process. Experimental results on industrial case studies illustrate the benefits of the approach.