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Conference Papers Year : 2018

Boosting transactional memory with stricter serializability


Transactional memory (TM) guarantees that a sequence of operations encapsulated into a transaction is atomic. This simple yet powerful paradigm is a promising direction for writing concurrent applications. Recent TM designs employ a time-based mechanism to leverage the performance advantage of invisible reads. With the advent of many-core architectures and non-uniform memory (NUMA) architectures, this technique is however hitting the synchronization wall of the cache coherency protocol. To address this limitation, we propose a novel and flexible approach based on a new consistency criteria named stricter serializability ($${\text {SSER}^+}$$SSER+). Workloads executed under $${\text {SSER}^+}$$SSER+ are opaque when the object graph forms a tree and transactions traverse it top-down. We present a matching algorithm that supports invisible reads, lazy snapshots, and that can trade synchronization for more parallelism. Several empirical results against a well-established TM design demonstrate the benefits of our solution
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Dates and versions

hal-01821500 , version 1 (22-06-2018)



Pierre Sutra, Patrick Marlier, Valerio Schiavoni, François Trahay. Boosting transactional memory with stricter serializability. 20th International Conference on Coordination Languages and Models (COORDINATION), Jun 2018, Madrid, Spain. pp.231-251, ⟨10.1007/978-3-319-92408-3_11⟩. ⟨hal-01821500⟩
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