Semi- and Fully-Random Access LUTs for Smooth Functions - VLSI-SoC: New Technology Enabler 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 Revised and Extended Selected Papers Access content directly
Conference Papers Year : 2020

Semi- and Fully-Random Access LUTs for Smooth Functions

Y. Serhan Gener
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Furkan Aydin
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  • PersonId : 1120101
Sezer Gören
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H. Fatih Ugurdag
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Look-Up Table (LUT) implementation of complicated functions often offers lower latency compared to algebraic implementations at the expense of significant area penalty. If the function is smooth, MultiPartite table method (MP) can circumvent the area problem by breaking up the implementation into multiple smaller LUTs. However, even some of these smaller LUTs may be big in high accuracy MP implementations. Lossless LUT compression can be applied to these LUTs to further improve area and even timing in some cases. The state-of-the-art in the literature decomposes the Table of Initial Values (TIV) of MP into a table of pivots and tables of differences from the pivots. Our technique instead places differences of consecutive elements in the difference tables and result in a smaller range of differences that fit in fewer bits. Constraining the difference of consecutive input values, hence semi-random access, allows us to further optimize designs. We also propose variants of our techniques with variable length coding. We implemented Verilog generators of MP for sine and exponential using conventional LUT as well as different versions of the state-of-the-art and our technique. We synthesized the generated designs on FPGA and found that our techniques produce up to 29% improvement in area, 11% improvement in timing, and 26% improvement in area-time product over the state-of-the-art.
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Dates and versions

hal-03476614 , version 1 (13-12-2021)





Y. Serhan Gener, Furkan Aydin, Sezer Gören, H. Fatih Ugurdag. Semi- and Fully-Random Access LUTs for Smooth Functions. 27th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2019, Cusco, Peru. pp.279-306, ⟨10.1007/978-3-030-53273-4_13⟩. ⟨hal-03476614⟩
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