Process Variability Impact on the SET Response of FinFET Multi-level Design - VLSI-SoC: New Technology Enabler 27th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration, VLSI-SoC 2019 Cusco, Peru, October 6–9, 2019 Revised and Extended Selected Papers Access content directly
Conference Papers Year : 2020

Process Variability Impact on the SET Response of FinFET Multi-level Design


Challenges were introduced in integrated circuits design due to the technology scaling. The evolution of integrated circuits has made them more susceptible to the radiation effects, besides increasing the manufacturing process variability. These challenges can lead to circuits operating outside their specification ranges. Transistor arrangement influences the performance of logic cells; complex logic gates can be used to minimize area, delay and power consumption. However, with the increasing relevance of nanometer challenges, it is necessary also to consider these factors at logic level design. This work explores different transistor arrangements for a set of logic functions at the layout level to evaluate the SET response under the process variability. The process variability is analyzed through the work-function fluctuations of the metal gate. The complex gate and the multi-level of NAND2 topologies, that implement the same function, were designed using the 7 nm FinFET ASAP7 Process Design Kit. Results show that the multi-level topology is more robust to the radiation effects at both ideal fabrication process and considering the process variability impact. The LETth value considering the multi-level topology is on average 55% higher than the values considering the complex topology. Moreover, all the logic functions analyzed independently of the topology are more sensitive to the SETs considering the impact of the process variability.
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hal-03476601 , version 1 (13-12-2021)





Leonardo H. Brendler, Alexandra L. Zimpeck, Cristina Meinhardt, Ricardo Reis. Process Variability Impact on the SET Response of FinFET Multi-level Design. 27th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC), Oct 2019, Cusco, Peru. pp.89-113, ⟨10.1007/978-3-030-53273-4_5⟩. ⟨hal-03476601⟩
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