Spin-Transfer-Torque Magnetic RAM (STT-MRAM) is a promising non-volatile memory technology due to its ultra-integration density capability, nanosecond speeds for reading and writing operations and CMOS/FinFET fabrication process compatibility. STT-MRAMs may be affected by manufacturing defects, which may be challenging to detect under process variations in deeply scaled semiconductor technologies. Because of this, the importance of test techniques to target defects in this emerging memory technology. In this work, an STT-MRAM bit-cell is presented with its states due to the magnetic orientation of the ferromagnetic layers. The read and write operations of an STT-MRAM cell, including the read and write circuits, are revised in the scope of this work. The write time definition for an STT-MRAM cell is also revised. A defect model is used to analyze the STT-MRAM cell under short defects in the presence of process variations. A Design-For-Test (DFT) circuit to detect short defects in the STT-MRAM cells is proposed. The proposed methodology is based on the observation that a short defect modifies the amplitude of the currents entering and leaving the memory cell. Hence, the current difference between the currents entering and leaving the memory cell is used to discriminate between good cells and defective cells. The proposed DFT circuitry is robust to process-induced parameters variations in the memory cell. In such a way, defects detection probabilities are increased, and a high-quality product can be guaranteed.