Modeling and Analysis of SLDL-Captured NoC Abstractions - System Level Design from HW/SW to Memory for Embedded Systems Access content directly
Conference Papers Year : 2017

Modeling and Analysis of SLDL-Captured NoC Abstractions

Ran Hao
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Nasibeh Teimouri
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Kasra Moazzemi
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Gunar Schirner
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  • PersonId : 1001408


With increasing number of IP cores, parallel communication architectures including NoCs have emerged for many-core systems. To efficiently architect NoCs, early analysis of crucial run-time metrics such as throughput, latency and saturation time is required. This requires abstract modeling of NoCs. Modeling abstraction, and consequently the modeling granularity impacts the accuracy and speed of simulation. While a fine-grained model will slowly lead more accurate information, a coarser model simulates faster and yields less accurate predictions. This paper first identifies possible levels of abstraction for NoC models and correlating captured features with the accuracy/speed trade-off. Second, this paper proposes two NoC models at different abstraction levels: a finer grained Bus-Functional Model (BFM), and a coarser Transaction-Level Model (TLM). The BFM updates the system status after any events happening during data unit transmission, while the TLM updates the system status at the end of data unit transmission.Our evaluation results show moving to higher abstraction (from BFM to TLM) gains 10x to 50x speedup at the cost of 10%–20% accuracy loss on average. Our analysis approach and results guide system architects in exploring NoC architectural alternatives and help identifying suitable abstract levels.
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hal-01854166 , version 1 (06-08-2018)





Ran Hao, Nasibeh Teimouri, Kasra Moazzemi, Gunar Schirner. Modeling and Analysis of SLDL-Captured NoC Abstractions. 5th International Embedded Systems Symposium (IESS), Nov 2015, Foz do Iguaçu, Brazil. pp.128-141, ⟨10.1007/978-3-319-90023-0_11⟩. ⟨hal-01854166⟩
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