Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving - System Level Design from HW/SW to Memory for Embedded Systems Access content directly
Conference Papers Year : 2017

Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving

Abstract

Hardware/software codesigns are often modeled with the system level design language SystemC. Especially for safety critical applications, it is crucial to guarantee that such a design meets its requirement. In this paper, we present an approach to formally verify SystemC designs using the UCLID satisfiability modulo theories (SMT) solver. UCLID supports finite precision bitvector arithmetics. Thus, we can handle SystemC designs on a bit-precise level, which enables us to formally verify deeply integrated hardware/software systems that comprise detailed hardware models. At the same time, we exploit UCLID’s ability to handle symbolic variables and use k-inductive invariant checking for SystemC designs. With this inductive approach, we can counteract the state space explosion problem, which model checking approaches suffer from. We demonstrate the practical applicability of our approach with a SystemC design that comprises a bit- and cycle-accurate model of a UART and software that reads data from the UART.
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hal-01854165 , version 1 (06-08-2018)

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Lydia Jass, Paula Herber. Bit-Precise Formal Verification for SystemC Using Satisfiability Modulo Theories Solving. 5th International Embedded Systems Symposium (IESS), Nov 2015, Foz do Iguaçu, Brazil. pp.51-63, ⟨10.1007/978-3-319-90023-0_5⟩. ⟨hal-01854165⟩
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