Low Latency FPGA Implementation of Izhikevich-Neuron Model - System Level Design from HW/SW to Memory for Embedded Systems Access content directly
Conference Papers Year : 2017

Low Latency FPGA Implementation of Izhikevich-Neuron Model


The Izhikevich’s simple model (ISM) for neural activity presents a good compromise between waveform quality and computational cost. FPGAs (Field Programmable Gate Array) are powerful, flexible, and inexpensive digital hardware that can implement such model. In this paper, we present a highly combinational, low latency implementation of ISM for FPGA. In the absence of official benchmark to compare different implementations, we propose two different metrics to compare the technical literature with our implementation. In this benchmark, we can implement a system that, when compared to the literature, has almost 1.5 times the number of digital neurons (DN), and latency more than 56 times smaller. This shows that our implementation is best suited for hybrid network systems and presents a fair performance for only-artificial networks.
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Dates and versions

hal-01854162 , version 1 (06-08-2018)





Vitor Bandeira, Vivianne L. Costa, Guilherme Bontorin, Ricardo Reis. Low Latency FPGA Implementation of Izhikevich-Neuron Model. 5th International Embedded Systems Symposium (IESS), Nov 2015, Foz do Iguaçu, Brazil. pp.210-217, ⟨10.1007/978-3-319-90023-0_17⟩. ⟨hal-01854162⟩
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