HMC and DDR Performance Trade-offs - System Level Design from HW/SW to Memory for Embedded Systems Access content directly
Conference Papers Year : 2017

HMC and DDR Performance Trade-offs

Paulo C. Santos
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Marco Alves
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Luigi Carro
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Abstract

The evolution of main memories, from SDR to the current DDR, presents multiple technological breakthroughs, but still far from the requirements of the processors. With the advent of Hybrid Memory Cube (HMC), a promise of high bandwidth with low energy consumption and less area may provide better efficiency than the traditional DDR modules. This is especially attractive for embedded systems. In this paper, we perform a comprehensive performance comparison between HMC and DDR memories, to understand the capabilities and limitations of both. Simulation results running SPEC-CPU2006 and SPEC-OMP2001 benchmarks show that applications with low memory pressure behave similarly with HMC or DDR. We make the new observation that HMC performs better than DDR specially for applications with a high memory pressure and low spatial data locality. However, for applications with a streaming behavior, commonly present in the embedded system domain, our experiments show that current HMC row-buffer specifications do not take advantage of the spatial locality present in those applications.
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hal-01854154 , version 1 (06-08-2018)

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Paulo C. Santos, Marco Alves, Luigi Carro. HMC and DDR Performance Trade-offs. 5th International Embedded Systems Symposium (IESS), Nov 2015, Foz do Iguaçu, Brazil. pp.159-171, ⟨10.1007/978-3-319-90023-0_13⟩. ⟨hal-01854154⟩
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