Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs - VLSI-SoC: Internet of Things Foundations Access content directly
Conference Papers Year : 2015

Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs

Nur A. Touba
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Abstract

Three Dimensional Integrated Circuits are an important new paradigm in which different dies are stacked atop one another, and interconnected by Through Silicon Vias (TSVs). Testing 3D-ICs poses additional challenges because of the need to transfer data to the non-bottom layers and the limited number of TSVs available in the 3D-ICs for the data transfer. A novel test compression technique is proposed that introduces the ability to share tester data across layers using daisy-chained decompressors. This improves the encoding of test patterns substantially, thereby reducing the amount of test data required to be stored on the external tester. In addition, an inter-layer serialization technique is proposed, which further reduces the number of TSVs required, using simple hardware to serialize and deserialize the test data. Experimental results are presented demonstrating the efficiency of the technique proposed.
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hal-01383725 , version 1 (19-10-2016)

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Sreenivaas S. Muthyala, Nur A. Touba. Efficient Utilization of Test Elevators to Reduce Test Time in 3D-ICs. 22th IFIP/IEEE International Conference on Very Large Scale Integration - System on a Chip (VLSI-SoC 2014), Oct 2014, Playa del Carmen, Mexico. pp.21-38, ⟨10.1007/978-3-319-25279-7_2⟩. ⟨hal-01383725⟩
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