FPGA-Based High-Speed Authenticated Encryption System - VLSI-SoC: FromAlgorithms to Circuits and System-on-Chip Design Access content directly
Conference Papers Year : 2013

FPGA-Based High-Speed Authenticated Encryption System


The Advanced Encryption Standard (AES) running in the Galois/Counter Mode of Operation represents a de facto standard in the field of hardware-accelerated, block-cipher-based high-speed authenticated encryption (AE) systems. We propose hardware architectures supporting the Ethernet standard IEEE 802.3ba utilizing different cryptographic primitives suitable for AE applications. Our main design goal was to achieve high throughput on FPGA platforms. Compared to previous works aiming at data rates beyond 100 Gbit/s, our design makes use of an alternative block cipher and an alternative mode of operation, namely Serpent and the offset codebook mode of operation, respectively. Using four cipher cores for the encryption part of the AE architecture, we achieve a throughput of 141 Gbit/s on an Altera Stratix IV FPGA. The design requires 39 kALMs and runs at a maximum clock frequency of 275 MHz. This represents, to the best of our knowledge, the fastest full implementation of an AE scheme on FPGAs to date. In order to make the design applicable in a real-world environment, we developed a custom-designed printed circuit board for the Stratix IV FPGA, suitable to process data with up to 100 Gbit/s.
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hal-01456959 , version 1 (06-02-2017)





Michael Muehlberghuber, Christoph Keller, Frank K. Gürkaynak, Norbert Felber. FPGA-Based High-Speed Authenticated Encryption System. 20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. pp.1-20, ⟨10.1007/978-3-642-45073-0_1⟩. ⟨hal-01456959⟩
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