CMOS Implementation of Threshold Gates with Hysteresis - VLSI-SoC: FromAlgorithms to Circuits and System-on-Chip Design Access content directly
Conference Papers Year : 2013

CMOS Implementation of Threshold Gates with Hysteresis

Farhad A. Parsan
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  • PersonId : 1000364
Scott C. Smith
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  • PersonId : 1000365

Abstract

NULL Convention Logic (NCL) is one of the mainstream asynchronous logic design paradigms. NCL circuits use threshold gates with hysteresis. In this chapter, the transistor-level CMOS design of NCL gates is investigated, and various gate styles are introduced and compared to each other. In addition, a novel approach to design static NCL gates is introduced. The new approach is based on integrating each pair of pull-up and pull-down transistor networks into one composite transistor network. The new static gates are then compared to the original ones in terms of delay, area, and energy consumption. It will be shown that the new gate style is significantly faster with negligible area and energy overhead.
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hal-01456957 , version 1 (06-02-2017)

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Farhad A. Parsan, Scott C. Smith. CMOS Implementation of Threshold Gates with Hysteresis. 20th International Conference on Very Large Scale Integration (VLSI-SoC), Aug 2012, Santa Cruz, CA, United States. pp.196-216, ⟨10.1007/978-3-642-45073-0_11⟩. ⟨hal-01456957⟩
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