Design of a 3rd Order 1.5-Bit Continuous-Time Fully Differential Sigma-Delta (ΣΔ) Modulator Optimized for a Class D Audio Amplifier Using Differential Pairs - Technological Innovation for the Internet of Things Access content directly
Conference Papers Year : 2013

Design of a 3rd Order 1.5-Bit Continuous-Time Fully Differential Sigma-Delta (ΣΔ) Modulator Optimized for a Class D Audio Amplifier Using Differential Pairs

Abstract

This paper presents a 3rd order 1.5-bit Continuous-Time Fully Differential ΣΔ modulator with distributed feedback for a class D audio amplifier, using BJT differential pairs to implement the integrator stages. By relying on simple gain blocks instead of operational amplifiers to build the loop filter, a simpler overall circuit is obtained, where the non-ideal effects are embedded in the loop filter transfer function. This leads to a more difficult design process for the loop filter circuit, solved through the use of an optimization procedure based on genetic algorithms. Simulations of the electrical circuit show that it is capable of achieving a SNDR value of 73.4 dB and THD+N of about -80 dB for a signal bandwidth of 20 kHz and a sampling frequency of 1.28 MHz.
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hal-01348811 , version 1 (25-07-2016)

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Nuno Pereira, João De Melo, Nuno Paulino. Design of a 3rd Order 1.5-Bit Continuous-Time Fully Differential Sigma-Delta (ΣΔ) Modulator Optimized for a Class D Audio Amplifier Using Differential Pairs. 4th Doctoral Conference on Computing, Electrical and Industrial Systems (DoCEIS), Apr 2013, Costa de Caparica, Portugal. pp.639-646, ⟨10.1007/978-3-642-37291-9_69⟩. ⟨hal-01348811⟩
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