A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole - VLSI-SoC: Forward-Looking Trends in IC and Systems Design Access content directly
Conference Papers Year : 2012

A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole

Aaron Do
  • Function : Author
  • PersonId : 1007197
Chirn Chye Boon
  • Function : Author
  • PersonId : 1007198
Anh Manh Do
  • Function : Author
  • PersonId : 1007200
Kiat Seng Yeo
  • Function : Author
  • PersonId : 1007201

Abstract

A simple method to tune the output pole of a passive mixer is proposed which leads to up to 33 dB improvement in an IEEE 802.15.4 standard compatible receiver’s IF section IIP3. This method is used in the design of an ultra-low power receiver front-end which consumes just 2.2 mW from a 1-V supply while achieving a SSB NF of approximately 9 dB. The energy-aware architecture allows for a 70 % reduction in the nominal power consumption (down to 0.7 mW) under strong signal conditions while improving the receiver’s IIP3 and not affecting the receiver’s input matching. The receiver is designed in a 0.18-μm RFCMOS technology.
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hal-01515991 , version 1 (28-04-2017)

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Aaron Do, Chirn Chye Boon, Manthena Vamshi Krishna, Anh Manh Do, Kiat Seng Yeo. A 1-V CMOS Ultralow-Power Receiver Front End for the IEEE 802.15.4 Standard Using Tuned Passive Mixer Output Pole. 18th International Conference on Very Large Scale Integration (VLSISOC), Sep 2010, Madrid, Spain. pp.1-21, ⟨10.1007/978-3-642-28566-0_1⟩. ⟨hal-01515991⟩
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