Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis - VLSI-SoC: Technologies for Systems Integration Access content directly
Conference Papers Year : 2011

Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis

Abstract

The design and implementation of a hardware accelerator dedicated to Binary Arithmetic Decoding Engine (BADE) is presented. This is the main module of the Context-Adaptive Binary Arithmetic Decoder (CABAD), as used in the H.264/AVC on-chip video decoders. We propose and implement a new approach for accelerating the decoding hardware of the significance map by providing the correct context for the regular hardware engine of the (CABAD). The design development was based on a large set of software experiments, which aimed at exploiting the characteristic behavior of the bitstream during decoding. The analysis gave new insights to propose a new hardware architecture to improve throughput of regular engines for significance map with low silicon area overhead. The proposed solution was described in VHDL and synthesized to standard cells in IBM 0.18 μm CMOS process. The results show that the developed architecture reaches 187 MHz with a non optimized physical synthesis.
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hal-01569361 , version 1 (26-07-2017)

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Dieison Antonello Deprá, Sergio Bampi. Techniques for Architecture Design for Binary Arithmetic Decoder Engines Based on Bitstream Flow Analysis. 17th International Conference on Very Large Scale Integration (VLSISOC), Oct 2009, Florianópolis, Brazil. pp.181-197, ⟨10.1007/978-3-642-23120-9_10⟩. ⟨hal-01569361⟩
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