Physical Design Issues in 3-D Integrated Technologies - VLSI-SoC: Design Methodologies for SoC and SiP Access content directly
Conference Papers Year : 2010

Physical Design Issues in 3-D Integrated Technologies

Abstract

Design techniques for three-dimensional (3-D) ICs considerably lag the significant strides achieved in 3-D manufacturing technologies. Advanced design methodologies for 2-D circuits are not sufficient to manage the added complexity caused by the third dimension. Consequently, design methodologies that efficiently handle the added complexity and inherent heterogeneity of 3-D circuits are necessary. These 3-D design methodologies should support robust and reliable 3-D circuits, while considering different forms of vertical integration, such as systems-in-package and 3-D ICs with fine grain vertical interconnections. The techniques described in this chapter address important physical design issues and fundamental interconnect structures in the 3-D design process.
Fichier principal
Vignette du fichier
03130008.pdf (318.09 Ko) Télécharger le fichier
Origin Files produced by the author(s)
Loading...

Dates and versions

hal-01054273 , version 1 (05-08-2014)

Licence

Identifiers

Cite

Vasilis F. Pavlidis, Eby G. Friedman. Physical Design Issues in 3-D Integrated Technologies. 19th IFIP WG 10.5/IEEE International Conference on Very Large Scale Integration (VLSI-SoC), Oct 2008, Rhodes Island, India. pp.1-21, ⟨10.1007/978-3-642-12267-5_1⟩. ⟨hal-01054273⟩
123 View
120 Download

Altmetric

Share

Gmail Mastodon Facebook X LinkedIn More